Chiplet-Knight

Modern processors increasingly adopt chiplet-based designs, assembling a system-on-chip from multiple heterogeneous dies manufactured by different vendors, potentially on different process nodes. This disaggregation offers substantial advantages in yield, cost, and specialisation, but introduces fundamental trust boundary challenges absent from monolithic designs.

As supply chains diversify and chiplets from different manufacturers are integrated into a single package, ensuring data confidentiality and integrity across die-to-die interconnects becomes a primary concern. Physical access attacks, software exploitation of cross-chiplet interfaces, and the loss of coherence as a reliable security boundary all demand new architectural primitives. The project specifically targets the problem of establishing a minimal, formally verifiable trusted computing base (TCB) when security-critical functions span multiple chiplets from potentially untrusted sources.

Chiplet-Knight investigates four interconnected research directions: (1) threat modelling and taxonomy of attack surfaces unique to chiplet integration, including UCIe and EMIB interconnect standards; (2) secure translation and access control mechanisms at the die-to-die boundary; (3) coherence hardening — adapting cache coherence protocols to resist cross-chiplet attacks; and (4) design and evaluation of a dedicated Security Support Unit at the die-to-die boundary. The goal is to enable high-performance modular designs that remain formally accountable and practically deployable, identifying which security properties can be enforced at the chiplet boundary and at what performance cost.